The present invention relates generally to semiconductor integrated circuit devices and, more particularly, to layout schemes of static random access memory (SRAM) cells. The invention also relates to semiconductor memory devices using such cells.
One-port SRAM cells with complementary metal oxide semiconductor (CMOS) configurations are typically designed so that each cell consists essentially of six separate transistors. An exemplary layout of such cells has been disclosed in, for example, JP-A-10-178110 (laid open on Jun. 30, 1998).
In the prior known SRAM cell layout, a semiconductive well region of P type conductivity with inverters formed therein is subdivided into two subregions, which are disposed on the opposite sides of an N-type well region while permitting a well boundary line to extend in a direction parallel to bit lines.
The quest for higher integration and ultra-fine patterning techniques in modern memory devices requires optical exposure apparatus or equipment to decrease in wave length of beams used therein. To this end, the equipment is designed to employ exposure beams of shorter wavelength, which have advanced from G line to I line, and further to excimer laser. Unfortunately the requirements for micro-patterning architectures grows more rapidly than technological advance in trend of shortening wavelengths in such equipment. In recent years, it is strictly required that micropatterning is done with the minimum device-feature length that shrinks to less than or equal to the wavelength of an exposure beam used. This minimum feature length shrinkage would result in the layout of IC components—here, memory cells—becoming more complicated in planar shape, which must require the use of irregular polygonal layout patterns including key-shaped components, in order to achieve the intended configuration of on-chip circuitry with enhanced accuracy. This makes it impossible or at least very difficult to microfabricate ultra-fine layout patterns while disadvantageously serving as the cause of destruction of the symmetry of memory cells.
Regrettably the prior art approach is associated with a need to curve or bend a diffusion layer into a complicated key-like shape for the purpose of making electrical contact with a substrate of the P-type well region. Thus, the prior art suffers from a problem as to degradation of the symmetrization of cell layout pattern, making difficult successful achievement of microfabrication architectures for higher integration densities.